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Distributed Logic Simulation: Time-First Evaluation Vs. Event-Driven Algorithms

Sundaram, S and Patnaik, LM (1996) Distributed Logic Simulation: Time-First Evaluation Vs. Event-Driven Algorithms. In: 9th International Conference on VLSI Design, 3-6 January 1996, Bangalore, India, pp. 307-310.

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Abstract

With the increasing complexity of VLSI circuits, simulation of digital circuits is becoming a more complex and time-consuming task. General purpose parallel processing machines are increasingly being used to speed up a variety of VLSI CAD applications. All previous works on mapping sequential logic simulation algorithms onto general purpose parallel machines were centered around using event-driven algorithm, and do not satisfactorily address the suitability of a particular sequential algorithm for parallel implementation. In this paper, we present analysis of two distributed simulation algorithms: the centralized-time event-driven algorithm and the time-first evaluation algorithm, mapped onto a network of workstations. We present results over a wide range of ISCAS85 and ISCAS89 benchmark circuits, to show that the time-first evaluation algorithm is likely to be a viable alternative to the event-driven algorithm in the domain of parallel logic simulation

Item Type: Conference Paper
Additional Information: 1995 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE
Department/Centre: Division of Information Sciences > Supercomputer Education & Research Centre
Division of Electrical Sciences > Computer Science & Automation (Formerly, School of Automation)
Date Deposited: 07 Sep 2007
Last Modified: 19 Sep 2010 04:37
URI: http://eprints.iisc.ernet.in/id/eprint/10863

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