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Synthesis of energy-efficient configurable processor arrays

Visvanathan, V and Ramanathan, S (1994) Synthesis of energy-efficient configurable processor arrays. In: First International Workshop on Parallel Processing:IWPP'94, 26-31 December 1994, Bangalore, India, pp. 627-632.

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Abstract

We present a methodology to synthesize processor arrays that can be configured within an application domain. These configurable processor arrays are much more energy-efficient than general purpose processor arrays, and are comparable in performance to their hard-wired counterparts. The synthesis methodology is applicable for CMOS technology and is based on elementary architectural transformations like retiming, slowdown, holdup and folding. As an illustration of the methodology, the technique is applied to synthesize an energy-efficient processor array for finite-impulse-response filtering, configurable for sample-rate and filter-order. In order to achieve energy-efficiency, a variable clock and power supply, generated by a phase-locked-loop, is used.

Item Type: Conference Paper
Additional Information: Copyright of this article belongs to Tata McGraw-Hill.
Department/Centre: Division of Information Sciences > Supercomputer Education & Research Centre
Date Deposited: 19 Sep 2007
Last Modified: 11 Jan 2012 08:43
URI: http://eprints.iisc.ernet.in/id/eprint/10970

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