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A modular systolic architecture for delayed least mean squares adaptive filtering

Visvanathan, V and Ramanathan, N (1995) A modular systolic architecture for delayed least mean squares adaptive filtering. In: of the 8th International Conference on VLSI Design, 4-7 Jan. 1995, New Delhi, India, pp. 332-337.

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Abstract

Existing systolic architectures for DLMS adaptive filtering, delay the coefficient adaptation by (N-1) or N input sampling periods for a filter of order N. Further, these architectures enforce an output latency of the same amount, which translates to a tracking delay. Using an alternate systolization technique, this paper presents a systolic DLMS adaptive filter architecture in which the need for the tracking delay is eliminated and the amount by which the coefficient adaptation needs to be delayed-for systolization-is reduced by half. This would imply significantly improved convergence behavior over those of previously reported architectures. The architecture supports the same maximum sampling rate as the fastest such architecture reported so far, while using only half as many multiply-accumulate processor modules

Item Type: Conference Paper
Additional Information: 1995 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE
Keywords: adaptive filters;convergence of numerical methods;least mean squares methods;pipeline processing;systolic arrays
Department/Centre: Division of Information Sciences > Supercomputer Education & Research Centre
Date Deposited: 24 Sep 2007
Last Modified: 19 Sep 2010 04:38
URI: http://eprints.iisc.ernet.in/id/eprint/10990

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