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High performance VLSI implementation for H.264 Inter/Intra prediction

Alle, Mythri and Biswas, J and Nandy, SK (2007) High performance VLSI implementation for H.264 Inter/Intra prediction. In: International Conference on Consumer Electronics:ICCE 2007, Digest of Technical Papers, 10-14 January 2007, Las Vegas, NV, pp. 1-2.

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Abstract

We provide a hardware realization of motion compensation and reconstruction (MCR) module for H.264 baseline profile. We synthesize the MCR module using UMC library in $0.13\hspace{2mm}\mu$ CMOS technology. Our implementation occupies an area of 94756 gates and operates at a frequency of 250 MHz.

Item Type: Conference Paper
Additional Information: Copyright 2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Keywords: CMOS integrated circuits;image reconstruction;motion;compensation;video coding;VLSI
Department/Centre: Division of Information Sciences > Supercomputer Education & Research Centre
Date Deposited: 14 Aug 2007
Last Modified: 19 Sep 2010 04:38
URI: http://eprints.iisc.ernet.in/id/eprint/11677

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