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Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding

Chandar, Subash and Mehendale, Mahesh and Govindarajan, R (2006) Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding. In: Journal of VLSI Signal Processing Systems, 44 (3). pp. 245-267.

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Abstract

In embedded control applications, system cost and power/energy consumption are key considerations. In such applications, program memory forms a significant part of the chip area. Hence reducing code size reduces the system cost significantly. A significant part of the total power is consumed in fetching instructions from the program memory. Hence reducing instruction fetch power has been a key target for reducing power consumption. To reduce the cost and power consumption, embedded systems in these applications use application specific processors that are fine tuned to provide better solutions in terms of code density, and power consumption. Further fine tuning to suit each particular application in the targeted class can be achieved through reconfigurable architectures. In this paper, we propose a reconfiguration mechanism, called Instruction Re-map Table, to re-map the instructions to shorter length code words. Using this mechanism, frequently used set of instructions can be compressed. This reduces code size and hence the cost. Secondly, we use the same mechanism to target power reduction by encoding frequently used instruction sequences to Gray codes. Such encodings, along with instruction compression, reduce the instruction fetch power. We enhance Texas Instruments DSP core TMS320C27x to incorporate this mechanism and evaluate the improvements on code size and instruction fetch energy using real life embedded control application programs as benchmarks. Our scheme reduces the code size by over 10% and the energy consumed by over 40%.

Item Type: Journal Article
Additional Information: Copyright of this article belongs to Springer Science
Keywords: code compression;embedded DSP systems;energy reduction;re-configurable architecture
Department/Centre: Division of Information Sciences > Supercomputer Education & Research Centre
Date Deposited: 26 May 2008
Last Modified: 19 Sep 2010 04:45
URI: http://eprints.iisc.ernet.in/id/eprint/14044

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