Banerjee, Subhasis and Surendra, G and Nandy, SK (2008) On the effectiveness of phase based regression models to trade power and performance using dynamic processor adaptation. In: Journal of Systems Architecture, 54 (8). pp. 797-815.
aaaa.pdf - Published Version
Restricted to Registered users only
Download (424Kb) | Request a copy
Microarchitecture optimizations, in general, exploit the gross program behavior for performance improvement. Programs may be viewed as consisting of different "phases" which are characterized by variation in a number of processor performance metrics. Previous studies have shown that many of the performance metrics remain nearly constant within a "phase". Thus, the change in program "phases" may be identified by observing the change in the values of these metrics. This paper aims to exploit the time varying behavior of programs for processor adaptation. Since the resource usage is not uniform across all program "phases", the processor operates at varying levels of underutilization. During phases of low available Instruction Level Parallelism (ILP), resources may not be fully utilized while in other phases, more resources may be required to exploit all the available ILP. Thus, dynamically scaling the resources based on program behavior is an attractive mechanism for power–performance trade-off. In this paper we develop per-phase regression models to exploit the phase behavior of programs and adequately allocate resources for a target power–performance trade-off. Modeling processor performance–power using such a regression model is an efficient method to evaluate an architectural optimization quickly and accurately. We also show that the per-phase regression model is better suited than an "unified" regression model that does not use phase information. Further, we describe a methodology to allocate processor resources dynamically by using regression models which are developed at runtime. Our simulation results indicate that average energy savings of 20% can be achieved with respect to a maximally configured system with negligible impact on performance for most of the SPEC-CPU and MEDIA benchmarks.
|Item Type:||Journal Article|
|Additional Information:||Copyright of this article belongs to Elsevier.|
|Keywords:||Processor microarchitecture;Program phases;Regression model.|
|Department/Centre:||Division of Information Sciences > Supercomputer Education & Research Centre|
|Date Deposited:||20 Oct 2008 05:51|
|Last Modified:||19 Sep 2010 04:51|
Actions (login required)