Jain, Pradeep and Jain, Yogesh and Gopinath, K (2002) A Region Based Framework for Combined Register Allocation and Instruction Scheduling for EPIC Architectures. IISc-CSA-2002-4.
The Trimaran compiler infrastructure has been developed for supporting state of art research in compiling Instruction Level Parallelism (ILP) architectures, especially those based on Explicitly Parallel Instruction Computing (EPIC) and for research in instruction scheduling, register allocation and machine-dependent optimizations. The current framework in Trimaran is not suitable for experimenting with techniques in which the instruction scheduling and register allocation interact. This is mainly due to the horizontal model of compilation employed in these optimizations where one optimization phase is carried out on all the regions of the function before proceeding to the next phase. The vertical model of compilation, in which several phases can be carried out simultaneously on a region before proceeding to the next region, is needed for exploiting more focussed optimizations. We have redesigned the framework for the ordering of execution of scheduling and register allocation phases in Trimaran to meet the above goals. Using the framework, we have combined instruction scheduling and register allocation by first using a pro list scheduler, then incorporating register pressure to make it sensitive to register allocation costs and nally making it pro We give the design of the framework and the performance results of our implementation.
|Item Type:||Departmental Technical Report|
|Keywords:||Trimaran Compiler Infrastructure;Meld Scheduling;Chekuri's Heuristic|
|Department/Centre:||Division of Electrical Sciences > Computer Science & Automation (Formerly, School of Automation)|
|Date Deposited:||01 Jun 2004|
|Last Modified:||19 Sep 2010 04:12|
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