Nagpal, Rahul and Srikant, YN (2004) A Graph Matching Based Integrated Scheduling Framework for Clustered VLIW Processors. In: 2004 International Conference on Parallel Processing Workshops. ICPP 2004, 15-18 August, Quebec,Canada, pp. 530-537.
Scheduling for clustered architectures involves spatial concerns (where to schedule) as well as temporal concerns (when to schedule) and various clustered VLIW configurations, connectivity types, and inter-cluster communication models present different performance trade-offs to a scheduler. The scheduler is responsible for resolving the conficting requirements of exploiting the parallelism offered by the hardware and limiting the communication among clusters to achieve better performance without stretching the overall schedule. This paper proposes a generic graph matching based framework that resolves the phase-ordering and fixedordering problems associated with scheduling on a clustered VLIW processor by simultaneously considering various scheduling alternatives of instructions. We observe approximately 16% and 28% improvement in the performance over an earlier integrated scheme and a phase-decoupled scheme respectively without extra code size enalty.
|Item Type:||Conference Paper|
|Additional Information:||C 1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.|
|Department/Centre:||Division of Electrical Sciences > Computer Science & Automation (Formerly, School of Automation)|
|Date Deposited:||14 Dec 2005|
|Last Modified:||19 Sep 2010 04:12|
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