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Realization of Multiple Valued Logic and Memory by Hybrid SETMOS Architecture

Mahapatra, Santanu and Ionescu, Adrian Mihai (2005) Realization of Multiple Valued Logic and Memory by Hybrid SETMOS Architecture. In: IEEE Transactions On Nanotechnology, 4 (6). pp. 705-714.

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Abstract

A novel complimentary metal-oxide-semiconductor (CMOS) single-electron transistor (SET) hybrid architecture, named SETMOS, is proposed, which offers Coulomb blockade oscillations and quasi-periodic negative differential resistance effects at much higher current level than the traditional SETs. The Coulomb blockade oscillation characteristics are exploited to realize the multiple valued (MV) literal gate and the periodic negative differential resistance behavior is utilized to implement capacitor-less multiple valued static random access memory (MV SRAM) cell. The SETMOS literal gate is then used to build up other MV logic building blocks, e.g., transmission gate, binary to MV logic encoder, and MV to binary logic decoder. Analytical SET model simulations are employed to verify the functionalities of the proposed MV logic and memory cells for quaternary logic systems. SETMOS MV architectures are found to be much faster and less temperature-sensitive than previously reported hybrid CMOS-SET based MV circuits.

Item Type: Journal Article
Additional Information: Copyright 2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Keywords: Single-Electron;Cmos;Transistor;Circuit;Cells
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly, (CEDT) Centre for Electronic Design & Technology)
Date Deposited: 10 Feb 2010 06:35
Last Modified: 19 Sep 2010 04:56
URI: http://eprints.iisc.ernet.in/id/eprint/17288

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