Ramanathan, S and Visvanathan, V and Nandy, SK (1999) A computational engine for multirate FIR digital filtering. In: Signal Processing, 79 (2). pp. 213-222.
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Digital filtering is a key computation in digital signal processing (DSP) applications. There exist a wide variety of high-performance portable systems that rely on embedded DSP systems to varying degrees. It is therefore necessary that such systems are both versatile and power efficient. In this paper, we propose a computational engine (CE) to serve as an ASIP implementing compute-intensive/power-critical multirate finite-impulse-response (FIR) digital filtering algorithms in embedded systems. The CE is programmable and comprises of data path and control path. Control sequences necessary to realize a particular filter operation can be programmed onto the control path of the CE. The versatality and efficacy of the proposed CE is demonstrated in this paper.
|Item Type:||Journal Article|
|Additional Information:||Copyright of this article belongs to Elsevier Science BV.|
|Keywords:||VLSI signal processing;VLSI architectures;Hardware accelerators;Application specific instruction-set processors (ASIP);Low-power VLSI;Digital; filtering; Multirate FIR digital filtering;Computational engines.|
|Department/Centre:||Division of Information Sciences > Supercomputer Education & Research Centre|
|Date Deposited:||02 Mar 2009 08:47|
|Last Modified:||19 Sep 2010 04:58|
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