Lakshminarayanan, Sanjay and Kanchan, RS and Tekwani, PN and Gopakumar, K (2006) Multilevel inverter with 12-sided polygonal voltage space vector locations for induction motor drive. In: Iee Proceedings-Electric Power Applications, 53 (3). pp. 411-419.
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Multilevel inverters are preferred over two-level inverters in high-voltage, high-power applications mainly because low-switching-frequency PWM schemes can be implemented with power devices of low-voltage ratings. Common multilevel inverter structures such as NPC, H-bridge and flying capacitor will produce a hexagonal voltage space vector structure. In the overmodulation range a multilevel inverter with a hexagonal voltage space vector structure will produce high amplitude 5th and 7th harmonic voltages in the output voltages. The maximum phase peak fundamental voltage is 0.637 Vdc in six-step mode operation (where Vdc is the radii of the hexagonal voltage space vector structure). A 12-sided polygonal voltage space vector structure will have a maximum phase peak fundamental voltage of 0.64 Vdc in the linear modulation range itself (where Vdc is the radii of the 12-sided polygonal voltage space vector structure), which is more than the output in six-step operation in the over-modulation range for a conventional multilevel structure. Also with a 12-sided polygonal space vector structure, an additional boost of the fundamental phase voltage is possible in the 12-step operation with the elimination of the 5th- and 7th- order harmonics (6n +/- 1, n = 1, 3, 5... etc). A multilevel inverter structure with 12-sided polygonal voltage space vector structure is proposed for an induction motor drive. The proposed inverter structure is realised by cascading three conventional two-level inverters. This makes the power bus structure very simple.
|Item Type:||Journal Article|
|Additional Information:||Copyright of this article belongs to Institution Engineering Technology.|
|Department/Centre:||Division of Electrical Sciences > Electronic Systems Engineering (Formerly, (CEDT) Centre for Electronic Design & Technology)|
|Date Deposited:||01 Apr 2009 07:15|
|Last Modified:||19 Sep 2010 05:24|
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