Nandy, Soumitra K and Patnaik, LM (1985) A study of placement algorithms through trial interchange of logic modules. In: Computer-Aided Design, 17 (5). pp. 210-214.
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Based on trial interchanges, this paper develops three algorithms for the solution of the placement problem of logic modules in a circuit. A significant decrease in the computation time of such placement algorithms can be achieved by restricting the trial interchanges to only a subset of all the modules in a circuit. The three algorithms are simulated on a DEC 1090 system in Pascal and the performance of these algorithms in terms of total wirelength and computation time is compared with the results obtained by Steinberg, for the 34-module backboard wiring problem. Performance analysis of the first two algorithms reveals that algorithms based on pairwise trial interchanges (2 interchanges) achieve a desired placement faster than the algorithms based on trial N interchanges. The first two algorithms do not perform better than Steinberg's algorithm1, whereas the third algorithm based on trial pairwise interchange among unconnected pairs of modules (UPM) and connected pairs of modules (CPM) performs better than Steinberg's algorithm, both in terms of total wirelength (TWL) and computation time.
|Item Type:||Journal Article|
|Additional Information:||The copyright of this article belongs to Elsevier Science|
|Keywords:||computation time; trial interchanges; placement technique; logic modules|
|Department/Centre:||Division of Electrical Sciences > Computer Science & Automation (Formerly, School of Automation)|
|Date Deposited:||17 Nov 2009 13:13|
|Last Modified:||19 Sep 2010 05:33|
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