ePrints@IIScePrints@IISc Home | About | Browse | Latest Additions | Advanced Search | Contact | Help

Linear time geometrical design rule checker based on quadtree representation of VLSI mask layouts

Nandy, SK and Patnaik, LM (1986) Linear time geometrical design rule checker based on quadtree representation of VLSI mask layouts. In: Computer-Aided Design, 18 (7). 380 -388.

[img] PDF
http___www.sciencedirect.com_science__ob=MImg&_imagekey=B6TYR-482B039-YK-1&_cdi=5625&_user=512776&_orig=search&_coverDate=09_30_1986&_sk=999819992&view=c&wchp=dGLzVtb-zSkzk&md5=f7f0e10a600a5b.pdf - Published Version
Restricted to Registered users only

Download (776Kb) | Request a copy
Official URL: http://www.sciencedirect.com/science?_ob=MImg&_ima...

Abstract

An efficient geometrical design rule checker is proposed, based on operations on quadtrees, which represent VLSI mask layouts. The time complexity of the design rule checker is O(N), where N is the number of polygons in the mask. A pseudoPascal description is provided of all the important algorithms for geometrical design rule verification.

Item Type: Journal Article
Additional Information: Copyright of this article belongs to Elsevier Science.
Keywords: Computer-aided design;Geometrical design rule checker; Quadtrees.
Department/Centre: Division of Information Sciences > Supercomputer Education & Research Centre
Date Deposited: 04 Sep 2009 03:20
Last Modified: 19 Sep 2010 05:34
URI: http://eprints.iisc.ernet.in/id/eprint/20880

Actions (login required)

View Item View Item