Nandy, SK and Patnaik, LM (1987) Algorithm for incremental compaction of geometrical layouts. In: Computer-Aided Design, 19 (2). pp. 257-265.
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In this paper, a new incremental algorithm for layout compaction is proposed. In addition to its linear time performance in terms of the number of rectangles in the layout, we also describe how incremental compaction can form a good feature in the design of a layout editor. The design of such an editor is also described. In the design of the editor, we describe how arrays can be used to implement quadtrees that represent VLSI layouts. Such a representation provides speed of data access and low storage requirements.
|Item Type:||Journal Article|
|Additional Information:||copy right of this article belongs to Elsevier Science.|
|Keywords:||computer-aided design;VLSI layout;compaction algorithm.|
|Department/Centre:||Division of Electrical Sciences > Computer Science & Automation (Formerly, School of Automation)|
|Date Deposited:||09 Jul 2009 05:23|
|Last Modified:||19 Sep 2010 05:35|
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