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An RNS based transform Architecture for H.264/AVC

Are, Raghunath Babu and Rajan, K (2008) An RNS based transform Architecture for H.264/AVC. In: IEEE Region 10 Conference (TENCON 2008), NOV 19-21, 2008, Hyderabad, INDIA, pp. 1743-1748.

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Abstract

This paper presents the architecture and the VHDL design of an integer 2-D DCT used in the H.264/AVC. The 2-D DCT computation is performed by exploiting it’s orthogonality and separability property. The symmetry of the forward and inverse transform is used in this implementation. To reduce the computation overhead for the addition, subtraction and multiplication operations, we analyze the suitability of carry-free position independent residue number system (RNS) for the implementation of 2-D DCT. The implementation has been carried out in VHDL for Altera FPGA. We used the negative number representation in RNS, bit width analysis of the transforms and dedicated registers present in the Logic element of the FPGA to optimize the area. The complexity and efficiency analysis show that the proposed architecture could provide higher through-put.

Item Type: Conference Paper
Additional Information: Copyright 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE
Keywords: Number system converter;high-speed realization;residue;binary.
Department/Centre: Division of Physical & Mathematical Sciences > Instrumentation and Applied Physics (Formally ISU)
Date Deposited: 04 Jan 2010 07:45
Last Modified: 19 Sep 2010 05:36
URI: http://eprints.iisc.ernet.in/id/eprint/21150

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