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Evaluating Compiler Support for Complexity Effective Network Processing

Rao, Pradeep H and Nandy, SK (2003) Evaluating Compiler Support for Complexity Effective Network Processing. In: Workshop on Complexity-Effective Design held in conjunction with the 30th International Symposium on Computer Architecture (ISCA), June 2003, San Diego, California. USA..

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Abstract

Statically scheduled processors are known to enable low complexity hardware implementations that lead to reduced design and verification time. However, statically scheduled processors are critically dependent on the compiler to exploit instruction level parallelism and deliver higher performance. In order to ascertain the suitability of statically scheduled processors for network processing (which constitutes a significant segment of the microprocessor industry), we evaluate the performance of aggressive compiler optimizations for networking applications. We perform our evaluations on two multiple issue processors that extensively exploit static scheduling: in-order superscalar and VLIW. Our results indicate that: (1) the compiler optimizations significantly improve packet throughput on both these processors and this improved throughput is comparable with that reported for agressive out-of-order superscalar processors, (2) the performance advantage of an in-order superscalar processor over a VLIW processor is less than 1.8%, suggesting VLIW processors for complexity-effective designs, and (3) the increase in performance due to doubling processor frequency is limited to a maximum of 37%, due to instruction and memory latencies.

Item Type: Conference Paper
Keywords: network processors;VLIW;compiler optimization
Department/Centre: Division of Information Sciences > Supercomputer Education & Research Centre
Division of Electrical Sciences > Computer Science & Automation (Formerly, School of Automation)
Date Deposited: 26 Nov 2004
Last Modified: 19 Sep 2010 04:17
URI: http://eprints.iisc.ernet.in/id/eprint/2367

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