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A Note on Easily Testable Realizations for Logic Functions

Kodandapani, KL (1974) A Note on Easily Testable Realizations for Logic Functions. In: IEEE Transactions on Computers, C23 (3). pp. 332-333.

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Abstract

It is shown that at most, n + 3 tests are required to detect any single stuck-at fault in an AND gate or a single faulty EXCLUSIVE OR (EOR) gate in a Reed-Muller canonical form realization of a switching function.

Item Type: Journal Article
Additional Information: Copyright 1974 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Electrical Sciences > Computer Science & Automation (Formerly, School of Automation)
Date Deposited: 17 Dec 2009 09:09
Last Modified: 19 Sep 2010 05:48
URI: http://eprints.iisc.ernet.in/id/eprint/24103

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