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Assessment of SET Logic Robustness Through Noise Margin Modeling

Sathe, Chaitanya and Dan, Surya Shankar and Mahapatra, Santanu (2008) Assessment of SET Logic Robustness Through Noise Margin Modeling. In: IEEE Transactions on Electron Devices, 55 (3). pp. 909-915.

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Abstract

A compact model for noise margin (NM) of single-electron transistor (SET) logic is developed, which is a function of device capacitances and background charge (zeta). Noise margin is, then, used as a metric to evaluate the robustness of SET logic against background charge, temperature, and variation of SET gate and tunnel junction capacitances (CG and CT). It is shown that choosing alpha=CT/CG=1/3 maximizes the NM. An estimate of the maximum tolerable zeta is shown to be equal to plusmn0.03 e. Finally, the effect of mismatch in device parameters on the NM is studied through exhaustive simulations, which indicates that a isin [0.3, 0.4] provides maximum robustness. It is also observed that mismatch can have a significant impact on static power dissipation.

Item Type: Journal Article
Additional Information: Copyright 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Keywords: Terms—Background charge;compact model;Coulomb blockade;noise margin (NM);single-electron transistor (SET).
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly, (CEDT) Centre for Electronic Design & Technology)
Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited: 08 Mar 2010 10:55
Last Modified: 19 Sep 2010 05:56
URI: http://eprints.iisc.ernet.in/id/eprint/25934

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