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A Petri net model for evaluating packet buffering strategies in a network processor

Girish, BC and Govindarajan, R (2007) A Petri net model for evaluating packet buffering strategies in a network processor. In: 4th International Conference on the Quantitative Evaluation of Systems, SEP 17-19, Edinburgh, SCOTLAND.

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Abstract

Previous studies have shown that buffering packets in DRAM is a performance bottleneck. In order to understand the impediments in accessing the DRAM, we developed a detailed Petri net model of IP forwarding application on IXP2400 that models the different levels of the memory hierarchy. The cell based interface used to receive and transmit packets in a network processor leads to some small size DRAM accesses. Such narrow accesses to the DRAM expose the bank access latency, reducing the bandwidth that can be realized. With real traces up to 30% of the accesses are smaller than the cell size, resulting in 7.7% reduction in DRAM bandwidth. To overcome this problem, we propose buffering these small chunks of data in the on chip scratchpad memory. This scheme also exploits greater degree of parallelism between different levels of the memory hierarchy. Using real traces from the internet, we show that the transmit rate can be improved by an average of 21% over the base scheme without the use of additional hardware. Further, the impact of different traffic patterns on the network processor resources is studied. Under real traffic conditions, we show that the data bus which connects the off-chip packet buffer to the micro-engines, is the obstacle in achieving higher throughput.

Item Type: Conference Paper
Additional Information: Copyright 2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE..
Department/Centre: Division of Information Sciences > Supercomputer Education & Research Centre
Date Deposited: 08 Mar 2010 09:52
Last Modified: 19 Sep 2010 05:56
URI: http://eprints.iisc.ernet.in/id/eprint/26009

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