Rajore, Ritesh and Garga, Ganesh and Jamadagni, HS and Nandy, SK (2008) Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture. In: 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, JUL 02-04, 2008, Leuven.
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In modern wireline and wireless communication systems, Viterbi decoder is one of the most compute intensive and essential elements. Each standard requires a different configuration of Viterbi decoder. Hence there is a need to design a flexible reconfigurable Viterbi decoder to support different configurations on a single platform. In this paper we present a reconfigurable Viterbi decoder which can be reconfigured for standards such as WCDMA, CDMA2000, IEEE 802.11, DAB, DVB, and GSM. Different parameters like code rate, constraint length, polynomials and truncation length can be configured to map any of the above mentioned standards. Our design provides higher throughput and scalable power consumption in various configuration of the reconfigurable Viterbi decoder. The power and throughput can also be optimized for different standards.
|Item Type:||Conference Paper|
|Additional Information:||Copyright 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.|
|Department/Centre:||Division of Electrical Sciences > Electronic Systems Engineering (Formerly, (CEDT) Centre for Electronic Design & Technology)|
|Date Deposited:||30 Mar 2010 07:27|
|Last Modified:||19 Sep 2010 05:58|
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