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Analytical Bounds on the Threads in IXP1200 Network Processor

Ramakrishna, STGS and Jamadagni, HS (2003) Analytical Bounds on the Threads in IXP1200 Network Processor. In: Proceedings of the Euromicro Symposium on Digital System Design (DSD’03), Sept 1 -6, 2003, Antalya, Turkey, pp. 426-429.

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Abstract

Increasing link speeds have placed enormous burden on the processing requirements and the processors are expected to carry out a variety of tasks. Network Processors (NP) [1] [2] is the blanket name given to the processors, which are traded for flexibility and performance. Network Processors are offered by a number of vendors; to take the main burden of processing requirement of network related operations from the conventional processors. The Network Processors cover a spectrum of design tradeoff, that span in between the custom ASIC and the general-purpose processors. IXP1200 (Intel’s network processor) is one among them. This paper focuses on deriving the analytical bounds on the optimum number of threads in IXP1200 at 1Gbps wire speed.

Item Type: Conference Paper
Additional Information: ©2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Keywords: Analytical Bounds;Threads;IXP1200;Network Processor
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly, (CEDT) Centre for Electronic Design & Technology)
Date Deposited: 25 Aug 2008
Last Modified: 19 Sep 2010 04:17
URI: http://eprints.iisc.ernet.in/id/eprint/2702

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