Ajayan, KR and Bhat, Navakanta (2010) Linear transconductor with flipped voltage follower in 130 nm CMOS. In: Analog Integrated Circuits and Signal Processing, 63 (2). pp. 321-327.
iopl.pdf - Published Version
Restricted to Registered users only
Download (495Kb) | Request a copy
This paper presents a modified design method for linear transconductor circuit in 130 nm CMOS technology to improve linearity, robustness against process induced threshold voltage variability and reduce harmonic distortion. Source follower in the adaptively biased differential pair (ABDP) linear transconductor circuit is replaced with flipped voltage follower to improve the efficiency of the tail current source, which is connected to a conventional differential pair. The simulation results show the performance of the modified circuit also has better speed, noise performance and common mode rejection ratio compared to the ABDP circuit.
|Item Type:||Journal Article|
|Additional Information:||Copyright of this article belongs to Springer.|
|Keywords:||CMOS analog circuits;Threshold voltage variability;Flipped voltage follower;Adaptive biasing;Linear transconductor|
|Department/Centre:||Division of Electrical Sciences > Electrical Communication Engineering|
|Date Deposited:||08 Jun 2010 07:08|
|Last Modified:||19 Sep 2010 06:00|
Actions (login required)