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Power Optimal Network-on-Chip Interconnect Design

Vikas, G and Kuri, Joy and Varghese, K (2009) Power Optimal Network-on-Chip Interconnect Design. In: IEEE International SOC Conference, SEP 09-11, 2009, Belfast, pp. 147-150.

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Abstract

A large part of today's multi-core chips is interconnect. Increasing communication complexity has made essential new strategies for interconnects, such as Network on Chip. Power dissipation in interconnects has become a substantial part of the total power dissipation. Techniques to reduce interconnect power have thus become a necessity. In this paper, we present a design methodology that gives values of bus width for interconnect links, frequency of operation for routers, in Network on Chip scenario that satisfy required throughput and dissipate minimal switching power. We develop closed form analytical expressions for the power dissipation, with bus width and frequency as variables and then use Lagrange multiplier method to arrive at the optimal values. We present a 4 port router in 90 nm technology library as case study. The results obtained from analysis are discussed.

Item Type: Conference Paper
Additional Information: Copyright 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly, (CEDT) Centre for Electronic Design & Technology)
Date Deposited: 03 Jun 2010 06:47
Last Modified: 19 Sep 2010 06:07
URI: http://eprints.iisc.ernet.in/id/eprint/28177

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