Singh, Sandeep B and Biswas, Jayanta and Nandy, SK (2006) A cost effective pipelined divider for double precision floating point number. In: 17th IEEE International Conference on Application-Specific Systems, Architectures and Processors, Steamboat Springs,, Sep 11-13, 2006, Steamboat Springs, CO, pp. 132-137.
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he growth of high-performance application in computer graphics, signal processing and scientific computing is a key driver for high performance, fixed latency; pipelined floating point dividers. Solutions available in the literature use large lookup table for double precision floating point operations.In this paper, we propose a cost effective, fixed latency pipelined divider using modified Taylor-series expansion for double precision floating point operations. We reduce chip area by using a smaller lookup table. We show that the latency of the proposed divider is 49.4 times the latency of a full-adder. The proposed divider reduces chip area by about 81% than the pipelined divider in  which is based on modified Taylor-series.
|Item Type:||Conference Paper|
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|Date Deposited:||31 Aug 2010 05:28|
|Last Modified:||19 Sep 2010 06:12|
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