Alle, Mythri and Biswas, J and Nandy, SK (2006) High performance VLSI architecture design for H.264 CAVLC decoder. In: 17th IEEE International Conference on Application-Specific Systems ArchiteSteamboat Springs,, Sep 11-13, 2006, Steamboat Springs, CO, pp. 317-322.
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H.264 video standard achieves high quality video along with high data compression when compared to other existing video standards. H.264 uses context-based adaptive variable length coding (CAVLC) to code residual data in Baseline profile. In this paper we describe a novel architecture for CAVLC decoder including coeff-token decoder, level decoder total-zeros decoder and run-before decoder UMC library in 0.13 mu CMOS technology is used to synthesize the proposed design. The proposed design reduces chip area and improves critical path performance of CAVLC decoder in comparison with . Macroblock level (including luma and chroma) pipeline processing for CAVLC is implemented with an average of 141 cycles (including pipeline buffering) per macroblock at 250MHz clock frequency. To compare our results with  clock frequency is constrained to 125MHz. The area required for the proposed architecture is 17586 gates, which is 22.1% improvement in comparison to . We obtain a throughput of 1.73 * 10(6) macroblocks/second, which is 28% higher than that reported in . The proposed design meets the processing requirement of 1080HD  video at 30frames/seconds.
|Item Type:||Conference Paper|
|Additional Information:||Copyright 2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.|
|Department/Centre:||Division of Information Sciences > Supercomputer Education & Research Centre|
|Date Deposited:||31 Aug 2010 05:22|
|Last Modified:||19 Sep 2010 06:12|
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