Bhat, Navakanta and Mukherjee, Sugato (2002) Yield and speed enhancement of semiconductor integrated circuits using post-fabrication transistor mismatch compensation circuitry. Patent Number(s) WO 02073658 A2. Patent Assignee(s) Indian Institute of Science.
A novel technique for the enhancement of yield and speed of semiconductor integrated circuits using post fabrication transistor mismatch compensation circuitry is proposed. The system is novel because it recognizes that no matter what, the transistor mismatch is statistical in nature and hence it is prudent to exploit the nature of the distribution to get fast and slow circuits rather than make all circuits slow to meet 60 design index. The system comprises of sense amplifier, multiplexer, delay elements, and provision for hardwiring fast and slow circuits during packaging. The sense amplifier firing path is split into slow and fast path and the multiplexer can select one of these. The memory circuits are tested after fabrication to assess whether they could be partitioned as slow or fast circuits and accordingly an appropriate path is selected by the multiplexer. This path is then hardwired during packaging by connecting the select input of multiplexer to VDD or GND.
|Department/Centre:||Division of Electrical Sciences > Electrical Communication Engineering|
|Date Deposited:||10 Jan 2007|
|Last Modified:||19 Sep 2010 04:18|
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