Mathias, PC and Patnaik, LM (1988) A systolic evaluator for linear, quadratic, and cubic expressions. In: Journal of Parallel and Distributed Computing, 5 (6). 729 -740.
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High-speed evaluation of a large number of linear, quadratic, and cubic expressions is very important for the modeling and real-time display of objects in computer graphics. Using VLSI techniques, chips called pixel planes have actually been built by H. Fuchs and his group to evaluate linear expressions. In this paper, we describe a topological variant of Fuchs' pixel planes which can evaluate linear, quadratic, cubic, and higher-order polynomials. In our design, we make use of local interconnections only, i.e., interconnections between neighboring processing cells. This leads to the concept of tiling the processing cells for VLSI implementation.
|Item Type:||Journal Article|
|Additional Information:||Copyright of this article belongs to Elsevier science.|
|Department/Centre:||Division of Electrical Sciences > Computer Science & Automation (Formerly, School of Automation)
Division of Chemical Sciences > Sophisticated Instruments Facility
|Date Deposited:||06 Sep 2010 07:08|
|Last Modified:||19 Sep 2010 06:16|
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