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Design and performance evaluation of a systolic architecture for hidden-surface removal

Ajjanagadde, Venkatramana G and Patnaik, LM (1988) Design and performance evaluation of a systolic architecture for hidden-surface removal. In: Computers & Graphics, 12 (1). pp. 71-74.

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Official URL: http://dx.doi.org/10.1016/0097-8493(88)90010-6

Abstract

In this paper, we propose a systolic architecture for hidden-surface removal. Systolic architecture is a kind of parallel architecture best known for its easy VLSI implementability. After discussing the design details of the architecture, we present the results of the simulation experiments conducted in order to evaluate the performance of the architecture.

Item Type: Journal Article
Additional Information: Copyright of this article belongs to Elsevier science.
Department/Centre: Division of Electrical Sciences > Computer Science & Automation (Formerly, School of Automation)
Date Deposited: 07 Sep 2010 07:31
Last Modified: 07 Sep 2010 07:31
URI: http://eprints.iisc.ernet.in/id/eprint/32082

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