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A fault-tolerant multi-transputer architecture

Kumar, Krishna R and Sinha, SK and Patnaik, LM (1993) A fault-tolerant multi-transputer architecture. In: Microprocessors and Microsystems, 17 (2). pp. 75-81.

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Official URL: http://dx.doi.org/10.1016/0141-9331(93)90074-H

Abstract

A new fault-tolerant multi-transputer architecture capable of tolerating failure of any one component in the system is described. In the proposed architecture the processing nodes are automatically reconfigured in the event of a fault and the computations continue from the stage where the fault occurred. The process of reconfiguration is transparent to the user, and the identity of the failed component is communicated to the user along with the results of computations. Parallel solution of a typical engineering problem involving solution of Laplace's equation by the boundary element method has been implemented. The performance of the architecture in the event of faults has been investigated.

Item Type: Journal Article
Additional Information: Copyright of this article belongs to Elsevier Science.
Keywords: Fault tolerance;multiprocessors;transputers.
Department/Centre: Division of Electrical Sciences > Electrical Engineering
Date Deposited: 31 Jan 2011 12:28
Last Modified: 31 Jan 2011 12:28
URI: http://eprints.iisc.ernet.in/id/eprint/35274

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