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A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array

Nandy, SK and Narayanan, R and Visvanathan, V and Sadayappan, P and Chauhan, PS (1993) A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array. In: 1993 International Conference on Parallel Processing, AUG 16-20, 1993, SYRACUSE UNIV, SYRACUSE, NY,.

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Abstract

In this paper we develop a multithreaded VLSI processor linear array architecture to render complex environments based on the radiosity approach. The processing elements are identical and multithreaded. They work in Single Program Multiple Data (SPMD) mode. A new algorithm to do the radiosity computations based on the progressive refinement approach[2] is proposed. Simulation results indicate that the architecture is latency tolerant and scalable. It is shown that a linear array of 128 uni-threaded processing elements sustains a throughput close to 0.4 million patches/sec.

Item Type: Conference Paper
Additional Information: Copyright 1993 IEEE. Personal use of this material is permitted.However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Information Sciences > Supercomputer Education & Research Centre
Date Deposited: 31 Jan 2011 08:34
Last Modified: 31 Jan 2011 08:34
URI: http://eprints.iisc.ernet.in/id/eprint/35321

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