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Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique

Jeyasingh, Rakesh Gnana David and Bhat, Navakanta and Amrutur, Bharadwaj (2011) Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique. In: IEEE Transactions on Very Large Scale Integration Systems, 19 (2). pp. 295-304.

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Abstract

The increasing variability in device leakage has made the design of keepers for wide OR structures a challenging task. The conventional feedback keepers (CONV) can no longer improve the performance of wide dynamic gates for the future technologies. In this paper, we propose an adaptive keeper technique called rate sensing keeper (RSK) that enables faster switching and tracks the variation across different process corners. It can switch upto 1.9x faster (for 20 legs) than CONV and can scale upto 32 legs as against 20 legs for CONV in a 130-nm 1.2-V process. The delay tracking is within 8% across the different process corners. We demonstrate the circuit operation of RSK using a 32 x 8 register file implemented in an industrial 130-nm 1.2-V CMOS process. The performance of individual dynamic logic gates are also evaluated on chip for various keeper techniques. We show that the RSK technique gives superior performance compared to the other alternatives such as Conditional Keeper (CKP) and current mirror-based keeper (LCR).

Item Type: Journal Article
Additional Information: Copyright of this article belongs to IEEE.
Keywords: Bias; keeper; process variation; rate sensing; wide OR
Department/Centre: Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited: 01 Mar 2011 11:27
Last Modified: 01 Mar 2011 11:27
URI: http://eprints.iisc.ernet.in/id/eprint/35818

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