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Compiler-assisted power optimization for clustered VLIW architectures

Nagpal, Rahul and Srikant, Y. N. (2011) Compiler-assisted power optimization for clustered VLIW architectures. In: Parallel Computing, 37 (1). pp. 42-59.

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Official URL: http://dx.doi.org/10.1016/j.parco.2010.08.005

Abstract

Clustered VLIW architectures solve the scalability problem associated with flat VLIW architectures by partitioning the register file and connecting only a subset of the functional units to a register file. However, inter-cluster communication in clustered architectures leads to increased leakage in functional components and a high number of register accesses. In this paper, we propose compiler scheduling algorithms targeting two previously ignored power-hungry components in clustered VLIW architectures, viz., instruction decoder and register file. We consider a split decoder design and propose a new energy-aware instruction scheduling algorithm that provides 14.5% and 17.3% benefit in the decoder power consumption on an average over a purely hardware based scheme in the context of 2-clustered and 4-clustered VLIW machines. In the case of register files, we propose two new scheduling algorithms that exploit limited register snooping capability to reduce extra register file accesses. The proposed algorithms reduce register file power consumption on an average by 6.85% and 11.90% (10.39% and 17.78%), respectively, along with performance improvement of 4.81% and 5.34% (9.39% and 11.16%) over a traditional greedy algorithm for 2-clustered (4-clustered) VLIW machine. (C) 2010 Elsevier B.V. All rights reserved.

Item Type: Journal Article
Additional Information: Copyright of this article belongs to Elsevier Science B.V.
Keywords: Scheduling; Clustered VLIW processors; Energy-aware scheduling
Department/Centre: Division of Electrical Sciences > Computer Science & Automation (Formerly, School of Automation)
Date Deposited: 09 Mar 2011 04:49
Last Modified: 09 Mar 2011 04:49
URI: http://eprints.iisc.ernet.in/id/eprint/35885

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