Shah, Jimit and Raghunandan, KS and Varghese, Kuruvilla (2010) Area Optimized H.264 Intra Prediction Architecture for 1080p HD Resolution. In: 21st IEEE International Conference on Application-Specific Systems, Architectures and Processors, JUL 07-09, 2010, Rennes, FRANCE.
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High performance video standards use prediction techniques to achieve high picture quality at low bit rates. The type of prediction decides the bit rates and the image quality. Intra Prediction achieves high video quality with significant reduction in bit rate. This paper present an area optimized architecture for Intra prediction, for H.264 decoding at HDTV resolution with a target of achieving 60 fps. The architecture was validated on Virtex-5 FPGA based platform. The architecture achieves a frame rate of 64 fps. The architecture is based on multi-level memory hierarchy to reduce latency and ensure optimum resources utilization. It removes redundancy by reusing same functional blocks across different modes. The proposed architecture uses only 13% of the total LUTs available on the Xilinx FPGA XC5VLX50T.
|Item Type:||Conference Paper|
|Additional Information:||Copyright 2006 IEEE. Personal use of this material is permitted.However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.|
|Keywords:||Intra prediction; H.264 Decoder; 1080p HD; FPGA; Virtex 5; Video Processing|
|Department/Centre:||Division of Electrical Sciences > Electronic Systems Engineering (Formerly, (CEDT) Centre for Electronic Design & Technology)|
|Date Deposited:||07 Mar 2011 08:43|
|Last Modified:||07 Mar 2011 08:43|
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