Yousif, MS and Das, CR and Thazhuthaveetil, MJ (1994) A Cache coherence protocol for MIN-based multiprocessors. In: Journal of Supercomputing , 8 (2). pp. 163-185.
In this paper we present a cache coherence protocol for multistage interconnection network (MIN)-based multiprocessors with two distinct private caches: private-blocks caches (PCache) containing blocks private to a process and shared-blocks caches (SCache) containing data accessible by all processes. The architecture is extended by a coherence control bus connecting all shared-block cache controllers. Timing problems due to variable transit delays through the MIN are dealt with by introducing Transient states in the proposed cache coherence protocol. The impact of the coherence protocol on system performance is evaluated through a performance study of three phases. Assuming homogeneity of all nodes, a single-node queuing model (phase 3) is developed to analyze system performance. This model is solved for processor and coherence bus utilizations using the mean value analysis (MVA) technique with shared-blocks steady state probabilities (phase 1) and communication delays (phase 2) as input parameters. The performance of our system is compared to that of a system with an equivalent-sized unified cache and with a multiprocessor implementing a directory-based coherence protocol. System performance measures are verified through simulation.
|Item Type:||Journal Article|
|Additional Information:||Copyright of this article belongs to Springer.|
|Keywords:||Caches;cache coherence;mean value analysis;multiprocessor system;multistage intercormection network;split cache.|
|Department/Centre:||Division of Electrical Sciences > Computer Science & Automation (Formerly, School of Automation)|
|Date Deposited:||03 Aug 2011 10:10|
|Last Modified:||03 Aug 2011 10:10|
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