Abhishek, A and Khan, Amanulla and Singh, Virendra and Saluja, Kewal K and Singh, Adit D (2010) Test Application Time Minimization for RAS using Basis Optimization of Column Decoder. In: International Symposium on Circuits and Systems Nano-Bio Circuit Fabrics and Systems (ISCAS 2010), MAY 30-JUN 02, 2010, Paris, FRANCE, pp. 2614-2617.
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Random Access Scan, which addresses individual flip-flops in a design using a memory array like row and column decoder architecture, has recently attracted widespread attention, due to its potential for lower test application time, test data volume and test power dissipation when compared to traditional Serial Scan. This is because typically only a very limited number of random ``care'' bits in a test response need be modified to create the next test vector. Unlike traditional scan, most flip-flops need not be updated. Test application efficiency can be further improved by organizing the access by word instead of by bit. In this paper we present a new decoder structure that takes advantage of basis vectors and linear algebra to further significantly optimize test application in RAS by performing the write operations on multiple bits consecutively. Simulations performed on benchmark circuits show an average of 2-3 times speed up in test write time compared to conventional RAS.
|Item Type:||Conference Paper|
|Additional Information:||Copyright 2010 IEEE. Personal use of this material is permitted.However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.|
|Department/Centre:||Division of Electrical Sciences > Electrical Communication Engineering
Division of Information Sciences > Supercomputer Education & Research Centre
|Date Deposited:||06 Apr 2011 12:33|
|Last Modified:||28 Jun 2011 12:24|
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