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Generating synchronizable test sequences based on finite-statemachine with distributed ports

Luo, G and Dssouli, R and Vonbochmann, G and Venkataram, P and Ghedamsi, A (1994) Generating synchronizable test sequences based on finite-statemachine with distributed ports. In: IFIP TC6/WG6.1 6th international workshop on protocol test systems, SEP 28-30, 1993 , PAU, France.

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Official URL: http://portal.acm.org/citation.cfm?id=648128.74784...

Abstract

In the area of testing communication systems, the interfaces between systems to be tested and their testers have great impact on test generation and fault detectability. Several types of such interfaces have been standardized by the International Standardization Organization (ISO). A general distributed test architecture, containing distributed interfaces, has been presented in the literature for testing distributed systems based on the Open Distributing Processing (ODP) Basic Reference Model (BRM), which is a generalized version of ISO distributed test architecture. We study in this paper the issue of test selection with respect to such an test architecture. In particular, we consider communication systems that can be modeled by finite state machines with several distributed interfaces, called ports. A test generation method is developed for generating test sequences for such finite state machines, which is based on the idea of synchronizable test sequences. Starting from the initial effort by Sarikaya, a certain amount of work has been done for generating test sequences for finite state machines with respect to the ISO distributed test architecture, all based on the idea of modifying existing test generation methods to generate synchronizable test sequences. However, none studies the fault coverage provided by their methods. We investigate the issue of fault coverage and point out a fact that the methods given in the literature for the distributed test architecture cannot ensure the same fault coverage as the corresponding original testing methods. We also study the limitation of fault detectability in the distributed test architecture.

Item Type: Conference Paper
Additional Information: Copyright of this article belongs to Elsevier Science publication B.V.
Department/Centre: Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited: 01 Apr 2011 06:35
Last Modified: 01 Apr 2011 06:35
URI: http://eprints.iisc.ernet.in/id/eprint/36502

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