Sarkar, S and Majumdar, AK (1991) Tagged systolic arrays. In: IEE Proceedings of Computers and Digital Techniques, 138 (5). pp. 289-294.
Design of systolic arrays from a set of nonlinear and nonuniform recurrence equations is discussed. A systematic method for deriving a systolic design in such cases is presented. A novel architectural idea, termed a tagged systolic array, is introduced. The design methodology described broadens the class of algorithms amenable for tagged systolic array implementation. The methodology is illustrated by deriving a systolic design for the fast Fourier transform.
|Item Type:||Journal Article|
|Additional Information:||Copyright of this article belongs to Institution of Electrical Engineers (IEE)|
|Keywords:||fast Fourier transforms;systolic arrays;tagged systolic array;VLSI|
|Department/Centre:||Division of Electrical Sciences > Computer Science & Automation (Formerly, School of Automation)|
|Date Deposited:||30 Sep 2005|
|Last Modified:||19 Sep 2010 04:20|
Actions (login required)