Jagadish, N and Kumar, Mohan J and Patnaik, LM (1989) An Efficient Scheme for Interprocessor Communication Using Dual-Ported RAMs. In: IEEE Micro, 9 (5). pp. 10-19.
An approach for interprocessor interconnection is described in which communication between the processor nodes involves writing into and reading from a common memory area. The communicating processors do not have to contend for a common bus as in the case of shared-memory systems, since they have independent access to the common memory units shared between them. Only the memory access time of the processors limits the communication speed. Processor-to-processor communication does not use intermediate buffers, input/output ports, or DMAs. The example of a three-dimensional cube is used to illustrate the advantages of this scheme. The implementation of the interprocessor communication scheme on a 64-node cube configuration is discussed.
|Item Type:||Journal Article|
|Additional Information:||Ã�Â©1989 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.|
|Department/Centre:||Division of Electrical Sciences > Computer Science & Automation (Formerly, School of Automation)|
|Date Deposited:||05 Oct 2005|
|Last Modified:||19 Sep 2010 04:20|
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