Gurunath, B and Biswas, Nripendra N (1989) An Algorithm for Multiple Output Minimization. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 8 (9). pp. 1007-1013.
A computer-aided design procedure for the minimization of multiple-output Boolean functions as encountered in the synthesis of VLSI logic circuits is presented. A fast technique for the determination of essential prime cubes without generating all the prime cubes is among the salient features of the algorithm. A new class of selective prime cubes called valid selective prime cubes is described. This class of prime cubes has proved to be a very powerful tool inasmuch as it guides the algorithm to the minimal set of selective prime cubes while encountering either an independent chain or an interconnected chain of cyclic prime cubes. In many cases, this avoids branching, which is computationally an expensive operation. The algorithm does not generate either the complement or all the prime cubes of the functions. Therefore, it is well suited to minimizing functions with a large complement size and/or a very high number of prime cubes. The algorithm has been implemented in Pascal and evaluated using a large number of programmable logic arrays (PLAs) including those of the Berkeley PLA test set. Results of comparison with ESPRESSO II and McBOOLE indicate that the program produces absolute minimal solutions in most of the cases and near-minimal solutions in a few others.
|Item Type:||Journal Article|
|Additional Information:||©1989 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.|
|Department/Centre:||Division of Electrical Sciences > Electrical Communication Engineering|
|Date Deposited:||06 Oct 2005|
|Last Modified:||19 Sep 2010 04:20|
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