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Systolic Evaluation of Polynomial Expressions

Mathias, PC and Patnaik, LM (1990) Systolic Evaluation of Polynomial Expressions. In: IEEE Transactions on Computers, 39 (5). pp. 653-665.

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Abstract

High-speed evaluation of a large number of polynomial expressions has potential applications in the modeling and real-time display of objects in computer graphics. Using VLSI techniques, chips called pixel planes have been built by Fuchs and his group to evaluate linear expressions on frame buffers. Extending the linear evaluation to quadratic evaluation, however, has resulted in the loss of regularity of interconnection among the cells. In this paper, we present two types of organizations for frame buffers of m \times m pixels: one, a single wavefront complex cell array requiring $O(m^2n)$ space and the other a simple cell multiple wavefront array with $O(m^2)$ area and $O(n^2)$ wavefronts. Both these organizations have two main advantages over the earlier proposed method. The cells and the interconnection among them are regular and hence are suitable for efficient VLSI implementation. The organization also permits evaluation of higher order polynomials.

Item Type: Journal Article
Additional Information: �©1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Keywords: computer graphics;polygon scan conversion;polynomial expression evaluation;systolic arrays;VLSI
Department/Centre: Division of Electrical Sciences > Computer Science & Automation (Formerly, School of Automation)
Division of Chemical Sciences > Sophisticated Instruments Facility
Date Deposited: 21 Oct 2005
Last Modified: 19 Sep 2010 04:20
URI: http://eprints.iisc.ernet.in/id/eprint/3878

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