ePrints@IIScePrints@IISc Home | About | Browse | Latest Additions | Advanced Search | Contact | Help

Synthesis of ASIPs for DSP algorithms

Ramanathan, S and Visvanathan, V and Nandy, SK (1999) Synthesis of ASIPs for DSP algorithms. In: Integration, the VLSI Journal, 28 (1). 13-32 .

[img] PDF
Synthesis_of_ASIPs_for.pdf - Published Version
Restricted to Registered users only

Download (618Kb) | Request a copy
Official URL: http://dx.doi.org/10.1016/S0167-9260(99)00009-7

Abstract

ASICs offer the best realization of DSP algorithms in terms of performance, but the cost is prohibitive, especially when the volumes involved are low. However, if the architecture synthesis trajectory for such algorithms is such that the target architecture can be identified as an interconnection of elementary parameterized computational structures, then it is possible to attain a close match, both in terms of performance and power with respect to an ASIC, for any algorithmic parameters of the given algorithm. Such an architecture is weakly programmable (configurable) and can be viewed as an application specific integrated processor (ASIP). In this work, we present a methodology to synthesize ASIPs for DSP algorithms. (C) 1999 Elsevier Science B.V. All rights reserved.

Item Type: Journal Article
Additional Information: Copyright of this article belongs to Elsevier Science.
Keywords: Digital Signal Processing (DSP);Architectural Synthesis; Pipelined Architectures;Systolic Architectures;Con"gurable Architectures;Application Speci"c Integrated Processors (ASIP)
Department/Centre: Division of Information Sciences > Supercomputer Education & Research Centre
Date Deposited: 30 Jun 2011 10:16
Last Modified: 30 Jun 2011 10:16
URI: http://eprints.iisc.ernet.in/id/eprint/38827

Actions (login required)

View Item View Item