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Accelerating multi-core simulators

Dani, Aparna Mandke and Varadarajan, Keshavan and Amrutur, Bharadwaj and Srikant, YN (2010) Accelerating multi-core simulators. In: ACM Symposium on Applied Computing, Mar.2010, New York, NY.

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Official URL: http://portal.acm.org/citation.cfm?id=1774582

Abstract

Simulation is an important means of evaluating new microarchitectures. With the invention of multi-core (CMP) platforms, simulators are becoming larger and more complex. However, with the availability of CMPs with larger caches and higher operating frequency, the wall clock time required for simulating an application has become comparatively shorter. Reducing this simulation time further is a great challenge, especially in the case of multi-threaded workload due to indeterminacy introduced due to simultaneously executing various threads. In this paper, we propose a technique for speeding multi-core simulation. The model of the processor core and cache are replaced with functional models, to achieve speedup. A timed Petri net model is used to estimate the execution time of the processor and the memory access latencies are estimated using hit/miss information obtained from the functional model of the cache. This model can be used to predict performance of data parallel applications or multiprogramming workload on CMP platform with various cache hierarchies and shared bus interconnect. The error in estimation of the execution time of an application is within 6%. The speedup achieved ranges between an average of 2x--4x over the cycle accurate simulator.

Item Type: Conference Paper
Additional Information: Copyright of this article belongs to ACM Press.
Keywords: Chip Multi-core;Instruction Set Simulator;Cache Simulator; Timed Petri-nets
Department/Centre: Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited: 20 Dec 2011 06:47
Last Modified: 20 Dec 2011 06:47
URI: http://eprints.iisc.ernet.in/id/eprint/39006

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