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Simultaneous MultiStreaming for complexity-effective VLIW architectures

Rao, Pradeep H and Nandy, SK and Kiran, Satya MNV (2003) Simultaneous MultiStreaming for complexity-effective VLIW architectures. In: Lecture Notes in Computer Science, 2823 . pp. 166-179.

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Abstract

Very Long Instruction Word (VLIW) architectures exploit instruction level parallelism (ILP) with the help of the compiler to achieve higher instruction throughput with minimal hardware. However, control and data dependencies between operations limit the available ILP, which not only hinders the scalability of VLIW architectures, but also result in code size expansion. Although speculation and predicated execution mitigate ILP limitations due to control dependencies to a certain extent, they increase hardware cost and exacerbate code size expansion. Simultaneous multistreaming (SMS) can significantly improve operation throughput by allowing interleaved execution of operations from multiple instruction streams. In this paper we study SMS for VLIW architectures and quantify the benefits associated with it using a case study of the MPEG-2 video decoder. We also propose the notion of virtual resources for VLIW architectures, which decouple architectural resources (resources exposed to the compiler) from the microarchitectural resources, to limit code size expansion. Our results for a VLIW architecture demonstrate that: (1) SMS delivers much higher throughput than that achieved by speculation and predicated execution, (2) the increase in performance due to the addition of speculation and predicated execution support over SMS averages around 12%. The minor increase in performance might not warrant the additional hardware complexity involved, and (3) the notion of virtual resources is very effective in reducing no-operations (NOPs) and consequently reduce code size with little or no impact on performance.

Item Type: Editorials/Short Communications
Additional Information: Copyright of this article belongs to Springer.
Department/Centre: Division of Information Sciences > Supercomputer Education & Research Centre
Date Deposited: 24 Aug 2011 08:03
Last Modified: 24 Aug 2011 08:03
URI: http://eprints.iisc.ernet.in/id/eprint/40196

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