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Unified Vdd Vth Optimization Based DVFM Controller for a Logic Block

Kannan, SA and Sreeram, NS and Amrutur, Bharadwaj S (2008) Unified Vdd Vth Optimization Based DVFM Controller for a Logic Block. In: IEEE International Conference on VLSI Design, Hyderabad, India, 4-8 Jan. 2008 , Hyderabad .

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Abstract

In this paper analytical expressions for optimal Vdd and Vth to minimize energy for a given speed constraint are derived. These expressions are based on the EKV model for transistors and are valid in both strong inversion and sub threshold regions. The effect of gate leakage on the optimal Vdd and Vth is analyzed. A new gradient based algorithm for controlling Vdd and Vth based on delay and power monitoring results is proposed. A Vdd-Vth controller which uses the algorithm to dynamically control the supply and threshold voltage of a representative logic block (sum of absolute difference computation of an MPEG decoder) is designed. Simulation results using 65 nm predictive technology models are given.

Item Type: Conference Paper
Additional Information: Copyright 2008 IEEE. Personal use of this material is permitted.However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited: 17 Oct 2011 07:05
Last Modified: 17 Oct 2011 07:05
URI: http://eprints.iisc.ernet.in/id/eprint/40634

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