Shareef, Mohammed and Nair, Pradeep and Amrutur, Bharadwaj (2008) Energy Reduction in SRAM using Dynamic Voltage and Frequency Management. In: IEEE International Conference on VLSI Design, Hyderabad, India, 4-8 Jan. 2008 , Hyderabad.
Energy_Reduction_in.pdf - Published Version
Restricted to Registered users only
Download (551Kb) | Request a copy
This paper describes a dynamic voltage frequency control scheme for a 256 X 64 SRAM block for reducing the energy in active mode and stand-by mode. The DVFM control system monitors the external clock and changes the supply voltage and the body bias so as to achieve a significant reduction in energy. The behavioral model of the proposed DVFM control system algorithm is described and simulated in HDL using delay and energy parameters obtained through SPICE simulation. The frequency range dictated by an external controller is 100 MHz to I GHz. The supply voltage of the complete memory system is varied in steps of 50 mV over the range of 500 mV to IV. The threshold voltage range of operation is plusmn100 mV around the nominal value, achieving 83.4% energy reduction in the active mode and 86.7% in the stand-by mode. This paper also proposes a energy replica that is used in the energy monitor subsystem of the DVFM system.
|Item Type:||Conference Paper|
|Additional Information:||Copyright 2008 IEEE. Personal use of this material is permitted.However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.|
|Keywords:||Delay Monitor;DVFM,Energy reduction;Energy monitor;Pareto optimal curve;Replica circuits;SRAM.|
|Department/Centre:||Division of Electrical Sciences > Electrical Communication Engineering|
|Date Deposited:||17 Oct 2011 07:03|
|Last Modified:||17 Oct 2011 07:03|
Actions (login required)