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Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations

Das, Bishnu Prasad and Janakiraman, V and Amrutur, Bharadwaj and Jamadagni, HS and Arvind, NV (2008) Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations. In: IEEE International Conference on VLSI Design, Hyderabad, India, 4-8 Jan. 2008, Hyderabad .

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Abstract

We investigate the feasibility of developing a comprehensive gate delay and slew models which incorporates output load, input edge slew, supply voltage, temperature, global process variations and local process variations all in the same model. We find that the standard polynomial models cannot handle such a large heterogeneous set of input variables. We instead use neural networks, which are well known for their ability to approximate any arbitrary continuous function. Our initial experiments with a small subset of standard cell gates of an industrial 65 nm library show promising results with error in mean less than 1%, error in standard deviation less than 3% and maximum error less than 11% as compared to SPICE for models covering 0.9- 1.1 V of supply, -40degC to 125degC of temperature, load, slew and global and local process parameters. Enhancing the conventional libraries to be voltage and temperature scalable with similar accuracy requires on an average 4x more SPICE characterization runs.

Item Type: Conference Paper
Additional Information: Copyright 2008 IEEE. Personal use of this material is permitted.However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Electrical Sciences > Electrical Communication Engineering
Date Deposited: 17 Oct 2011 07:01
Last Modified: 17 Oct 2011 07:01
URI: http://eprints.iisc.ernet.in/id/eprint/40639

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