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A Systematic Approach to Synthesis of Verification Test-suites for Modular SoC Designs

Surendran, Sudhakar and Parekhji, Rubin and Govindarajan, R (2008) A Systematic Approach to Synthesis of Verification Test-suites for Modular SoC Designs. In: In Proc. of the 21st Annual IEEE SoC Conference, (SoCC-08), Newport Beach, CA, USA, 17-20 Sept. 2008 , Newport Beach, CA .

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Abstract

Verification is one of the important stages in designing an SoC (system on chips) that consumes upto 70% of the design time. In this work, we present a methodology to automatically generate verification test-cases to verify a class of SoCs and also enable re-use of verification resources created from one SoC to another. A prototype implementation for generating the test-cases is also presented.

Item Type: Conference Paper
Additional Information: Copyright 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Department/Centre: Division of Electrical Sciences > Computer Science & Automation (Formerly, School of Automation)
Date Deposited: 23 Sep 2011 08:58
Last Modified: 23 Sep 2011 08:58
URI: http://eprints.iisc.ernet.in/id/eprint/40723

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