Bhat, MS and Jamadagni, HS (2005) Static Power Minimization in Current-Mode Circuits. In: Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005, 18-21 January, China, Vol.2, 1220 -1223.
We propose a method involving selective signal gating to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present an approximation model for current in, a current comparator circuit. Power reduction is achieved by turning off the redundant comparator circuits using a switch-architecture. Simulations are carried-out for current-mode flash ADC designs and literal generating circuits for MVL to validate the method.
|Item Type:||Conference Paper|
|Additional Information:||©1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.|
|Department/Centre:||Division of Electrical Sciences > Electronic Systems Engineering (Formerly, (CEDT) Centre for Electronic Design & Technology)|
|Date Deposited:||23 Nov 2005|
|Last Modified:||19 Sep 2010 04:21|
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