Tudu, Jaynarayan and Larsson, Erik and Singh, Virendra and Singh, Adit (2009) Capture Power Reduction for Modular System-on-Chip Test. In: 14th IEEE VLSI Design and Test Symposium (VDAT), Bangalore.
Full text not available from this repository.| Item Type: | Conference Paper |
|---|---|
| Department/Centre: | Division of Information Sciences > Supercomputer Education & Research Centre |
| Date Deposited: | 14 Dec 2011 05:24 |
| Last Modified: | 14 Dec 2011 05:24 |
| URI: | http://eprints.iisc.ernet.in/id/eprint/41258 |
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