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A Simulation Based Study and Analysis of Double Gate Tunnel FET Performance for Low Stand-By Power Applications

Patel, Nayan B and Mahapatra, Santanu (2007) A Simulation Based Study and Analysis of Double Gate Tunnel FET Performance for Low Stand-By Power Applications. In: 11th VDAT Symposium - August 8-11, 2007 - Kolkata, August 8-11, Kolkata.

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Abstract

The conventional metal oxide semiconductor field effect transistor (MOSFET)may not be suitable for future low standby power (LSTP) applications due to its high off-state current as the sub-threshold swing is theoretically limited to 60mV/decade. Tunnel field effect transistor (TFET) based on gate controlled band to band tunneling has attracted attention for such applications due to its extremely small sub-threshold swing (much less than 60mV/decade). This paper takes a simulation approach to gain some insight into its electrostatics and the carrier transport mechanism. Using 2D device simulations, a thorough study and analysis of the electrical parameters of the planar double gate TFET is performed. Due to excellent sub-threshold characteristics and a reverse biased structure, it offers orders of magnitude less leakage current compared to the conventional MOSFET. In this work, it is shown that the device can be scaled down to channel lengths as small as 30 nm without affecting its performance. Also, it is observed that the bulk region of the device plays a major role in determining the sub-threshold characteristics of the device and considerable improvement in performance (in terms of ION/IOFF ratio) can be achieved if the thickness of the device is reduced. An ION/IOFF ratio of 2x1012 and a minimum point sub-threshold swing of 22mV/decade is obtained.

Item Type: Conference Paper
Related URLs:
Additional Information: Copyright of this article belongs to Nano Scale Device Research Lab.
Keywords: Sub-threshold Swing;Tunnel Transistor;Band to band tunneling
Department/Centre: Division of Electrical Sciences > Electronic Systems Engineering (Formerly, (CEDT) Centre for Electronic Design & Technology)
Date Deposited: 11 Oct 2011 09:01
Last Modified: 14 Nov 2013 12:23
URI: http://eprints.iisc.ernet.in/id/eprint/41354

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